Researching on the development of hardware implementation solution for the context - Adaptive binary arithmetic coder in the hevc standard

 MINISTRY OF EDUCATION AND TRANING MINISTRY OF DEFENSE 
ACADEMY OF MILITARY SCIENCE AND TECHNOLOGY 
TRAN DINH LAM 
RESEARCHING ON THE DEVELOPMENT OF 
HARDWARE IMPLEMENTATION SOLUTION FOR THE 
CONTEXT-ADAPTIVE BINARY ARITHMETIC CODER 
IN THE HEVC STANDARD 
Ph.D. THESIS IN ENGINEERING 
Ha Noi - 2021 
MINISTRY OF EDUCATION AND TRANING MINISTRY OF DEFENSE 
ACADEMY OF MILITARY SCIENCE AND TECHNOLOGY 
TRAN DINH LAM 
RESEARCHING ON THE DEVELOPMENT OF 
HARDWARE IMPLEMENTATION SOLUTION FOR THE 
CONTEXT-ADAPTIVE BINARY ARITHMETIC CODER 
IN THE HEVC STANDARD 
Specialization: Electronic engineering 
Code: 9 52 02 03 
Ph.D. THESIS IN ENGINEERING 
SCIENTIFIC SUPERVISOR: 
ASSOC. PROF. DR. TRAN XUAN TU 
Ha Noi - 2021 
i 
STATEMENT OF AUTHORSHIP 
Except where reference is made in the text of the thesis, this thesis 
contains no material published elsewhere or extracted in whole or in part from 
a thesis or any other degree or diploma. No other person’s work has been used 
without acknowledgment in the main text of the thesis. This thesis has not 
been submitted for the award of any degree or diploma in any other tertiary 
institution. 
Hanoi, Date month year 2021 
 Author 
 Tran Dinh Lam 
ii 
ACKNOWLEDGEMENTS 
During the research work and fulfill the Ph.D thesis, I have received 
tremendous support, facilitated from Institute of Electronics, Training 
Department of Academy of Military Science and Technology. I would like to 
express my sincere thanks to the representatives of the organisations. 
I would like to express my deep gratitude to my supervisor, Assoc. Prof., 
Dr. Tran Xuan Tu for his continuous support, encouragement and supervision 
throughout my research work and the completion of this thesis. 
I would also like to extend my gratitude to the teachers in the Institute of 
Electronics, the Academy of Military Science and Technology for their 
valuable suggestions during my research. 
I would like to thank the teachers and other members of VNU Key 
Labpratory for Smart Integrated Systems (SISLAB) for their comments and 
supports throughout my PhD work. 
I would like to thank my colleagues and friends, who always support and 
encourage me during taking the PhD. 
Last but not least, I would like to express my sincere gratitude to my 
family, relatives who have shared and always encouraged me to overcome 
difficulties to successfully complete this thesis. 
Hanoi, Date month year 2021 
 Author 
 Tran Dinh Lam 
iii 
CONTENTS 
Page 
LIST OF ABBREVIATIONS .....vi 
LIST OF TABLES.......ix 
LIST OF FIGURES.......x 
INTRODUCTION.....1 
Chapter 1. OVERVIEW OF THE CONTEXT ADAPTIVE BINARY 
ARITHMETIC CODING IN THE HEVC STANDARD ................................. 7 
1.1. Development history of video encoding standard .................................... 7 
1.1.1. The necessity of video encoding .................................................... 7 
1.1.2. The evolution of video compression standards .............................. 9 
1.2. Principle of video encoding in the HEVC standard ................................ 10 
1.2.1. The architecture of the HEVC encoder ........................................ 10 
1.2.2. The improvements of encoding algorithms in the HEVC 
standard ...................................................................................................... 11 
1.2.3. Principle and architecture of a CABAC encoder for HEVC ....... 19 
1.3. Overview on the development of CABAC encoder in HEVC 
standard. .......................................................................................................... 25 
1.3.1. Research directions of hardware development towards 
realizing CABAC in HEVC standard for video applications ..................... 26 
1.3.2. Solutions to improve encoding throughput .................................. 29 
1.3.3. High efficient hardware architecture ............................................ 35 
1.3.4. Conclusion on research and development, thesis research 
orientation. .................................................................................................. 38 
1.4. Chapter conclusion .................................................................................. 39 
Chapter 2. PROPOSE HARDWARE DESIGN SOLUTIONS TO 
IMPROVE THE EFFICIENCY OF THE CABAC ENCODER IN THE 
HEVC STANDARD ....................................................................................... 41 
2.1. Proposed funtional block diagram of CABAC encoder architecture ...... 41 
2.2. Binarizer ................................................................................................... 43 
2.2.1. Data statistics of Binarizer ................................................................ 43 
2.2.2. The structure of residual syntax elements ......................................... 45 
iv 
2.2.3. The drawbacks of multi-core syntax element generation 
architecture .................................................................................................. 49 
2.2.4. The “one scan for multiple syntax element generation” technique .. 52 
2.2.5. The solution for binarization of last_sig_coeff_post syntax 
element ........................................................................................................ 56 
2.3. Binary arithmetic encoding (BAE) module ............................................. 59 
2.3.1. The context-adaptive encoding algorithm ........................................ 60 
2.3.2. Algorithm modification for simultaneously encoding multi 
bypass bins .................................................................................................. 63 
2.3.3. The hardware solution for four-stage BAE architecture ................... 65 
2.3.4. Proposed architecture for hardware savings ..................................... 67 
2.4. Chapter conclusion ................................................................................... 71 
Chapter 3. SIMULATION, VERIFICATION, IMPLEMENTATION 
AND EVALUATION OF THE RESEARCH RESULTS .............................. 73 
3.1. Building the simulation software model .................................................. 74 
3.1.1. HM Test Model ................................................................................. 74 
3.1.2. Building the software model for verification .................................... 75 
3.2. Proposing the Hardware-Software co-simulation model for 
verification the research results ....................................................................... 76 
3.2.1. CodecVisa tool .................................................................................. 76 
3.2.2. The experimental model for verification of the results..................... 78 
3.3. Simulation and verification of proposed design solutions ....................... 84 
3.4. Synthesis, simulation and evaluation of parameters of proposed 
design solutions ............................................................................................... 88 
3.4.1. Report of performance parameters for residual syntax element 
generation module ....................................................................................... 89 
3.4.2. Report of performance parameters for Binarization module ............ 90 
3.4.3. Report of performance parameters for Binary Arithmetic 
Encoding module ........................................................................................ 91 
3.5. Summary of proposed research results and comparisons with related 
state-of-the-art results ...................................................................................... 92 
3.6. Chapter conclusion ................................................................................... 95 
CONCLUSION ............................................................................................... 96 
v 
LIST OF SCIENTIFIC PUBLICATIONS ...................................................... 99 
BIBLIOGRAPHY ......................................................................................... 100 
vi 
LIST OF ABBREVIATIONS 
AI All Intra 
ASIC Application Specific Integrated Circuit 
AVC Advanced Video Coding 
BAE Binary Arithmetic Encoder 
BIBO Block-In-Block-Out 
CABAC Context Adaptive Binary Arithmetic Coding 
CALR Coefficient Absolute Level Remaining 
CALVC Context Adaptive Variable Length Coding 
CB Coding Block 
CG Coefficient Group 
CM Context Modeler 
CODEC COding DECoding 
CTB Coding Tree Block 
CTU Coding Tree Unit 
CU Coding Unit 
DCT Discrete Cosine Transform 
DST Discrete Sine Transform 
EGk Exponential Golomb k-order 
FIFO First In First Out 
FL Fixed Length 
FSM Finite State Machine 
vii 
HDTV High Definition TeleVision 
HEVC High Efficient Video Coding 
ISO/IEC International Organization for Standardization/ International 
Electrotechnical Commission 
ITU-T International Telecommunication Union – 
Telecommunication 
JCT-VC Joint Collaborative Team – Video Coding 
LD Low Delay 
LPS Least Probably Symbol 
LUT Look Up Table 
MBBS Multi Bypass Bin Spliting 
MC Motion Compensation 
MRSET Multiple Residual Syntax Element Treatment 
MPEG Moving Picture Expert Group 
MPS Most Probably Symbol 
MV Motion Vector 
PB Prediction Block 
PISO Parallel In Serial Out 
PU Prediction Unit 
RD Random Access 
rLPS range Least Probably Symbol 
RTL Register Transfer Level 
SAO Sample Adaptive Offset 
viii 
SE Syntax Element 
TB Transform Block 
TC Transform Coefficient 
TU Transform Unit 
UHD Ultra High Definition 
UHD-TV Ultra High Definition-TeleVision 
VHDL Very-high-speed-integrated-circuit Hardware Description 
Language 
VLSI Very Large Scale Integration 
WPP Wave-front Parallel Processing 
ix 
LIST OF TABLES 
Page 
Table 1.1. The development of video compression standards [4] .................... 9 
Table 1.2. Comparison of the state-of-the-art works ...................................... 36 
Table 2.1. Statistics of input data type of CABAC .......................................... 44 
Table 2.2. Major bins contributors among HEVC data hierarchy [42] ......... 45 
Table 2.3. Set of Syntax Element for 4 4 TU .................................................. 47 
Bảng 2.4. Binarization method for last_sig_coeff_x và last_sig_coeff_y ....... 57 
Table 2.5. Illustration of relations of EPbits and EPlen to input bypass bins ... 
 ......................................................................................................................... 64 
Table 3.1. data formats in CABAC encoder.................................................... 79 
Figure 3.2. Video Test Sequences for verification of proposed designs ......... 84 
Table 3.3. Statistical report of the hardware resource ................................... 89 
Table 3.4. Detailed report of area cost ........................................................... 89 
Table 3.5. Statistical report of power distribution (W) ................................ 90 
Table 3.6. Detailed report of power consumption (W) ................................ 90 
Table 3.7. Statistical report of the hardware resource ................................... 90 
Tale 3.8. Detailed report of area cost ............................................................. 90 
Table 3.9. Statistical report of power consumption (W) .............................. 91 
Table 3.10. Detailed report of power consumption ........................................ 91 
Table 3.11. Statistical report of the hardware resource ................................. 91 
Table 3.12. Detailed report of area cost ......................................................... 91 
Table 3.13. Statistical report of power consumption (W) ............................ 91 
Table 3.14. Detailed report of power consumption ........................................ 92 
Table 3.15. Comparisons with the state-of-the-art residual syntax element 
generation and binarization modules ............................................................. 93 
Table 3.16. Comparison with the state-of-the-art works in implementation of 
BAE module ..................................................................................................... 95 
x 
LIST OF FIGURES 
Page 
Figure 1.1. General architecture of a video storage, transmission system. ..... 8 
Figure 1.2. Block diagram of HEVC encoder [57]. ....................................... 11 
Figure 1.3. Block division technique of HEVC and H.264/AVC standards. .. 12 
Figure 1.4. The partition and organization techniques of video data in HEVC.
 ......................................................................................................................... 13 
Figure 1.5. The numbering and ordering technique of an encoding CTU. .... 14 
Figure 1.6. Inter-image prediction in HEVC standard. .................................. 15 
Figure 1.7. Dividing methods of PBs in HEVC [6]. ....................................... 16 
Figure 1.8. Comparison of intra prediction between HEVC and H.264/AVC 
[15]. ................................................................................................................. 17 
Figure 1.9. Frequency-Time Transform in HEVC [57]. ................................. 17 
Figure 1.10. Data blocks are divided in transform [57]. ............................... 18 
Figure 1.11. Application of the Tile for parallel processing of pixel blocks. . 19 
Figure 1.12. WPP data processing [16]. ........................................................ 19 
Figure 1.13. CABAC encoder block diagram [55]. ........................................ 20 
Figure 1.14. Encoded bit stream structure of a data slice segment [60]. ...... 21 
Figure 1.15. Encoding algorithm of regular coded bin. ................................. 22 
Figure 1.16.Recursive sub-interval division principle based on bin 
probabilities. ................................................................................................... 24 
Figure 1.17. Block diagram of the CABAC hardware architecture [57]. ...... 25 
Figure 1.18. Architecture of multi-core CABAC encoder [38]. ..................... 29 
Figure 1.19. Architecture of CABAC encoder with parallel bypass bin 
processing [59]. .............................................................................................. 30 
Hình 1.20. Functional block diagram of the Binarizer [55]. ......................... 31 
Hình 1.21. Kiến trúc chức năng bộ biến đổi nhị phân đa lõi [1]. .................. 31 
Figure 1.22. The architecture of Heterogeneous Binarizer [59]. .................. 32 
Figure 1. 23. Hardware architecture of four-stage pipeline BAE module ..... 33 
Figure 1.24. The hardware architecture for multi-bin BAE module .............. 34 
Figure 1.25. Parallel four-core architecture for Syntax element generation 
module [42]. ....................... ... ient CABAC Hardware Implementations in 
HEVC Standard,” VNU Journal of Computer Science and Communication 
Engineering, vol. 35, no. 2, pp. 1-21, 2019. 
2. Quang-Linh Nguyen, Dinh-Lam Tran, Duy-Hieu Bui, Duc-Tho Mai 
and Xuan-Tu Tran, “Efficient Binary Arithmetic Encoder for HEVC with 
Multiple Bypass Bin Processing,” in The 7th IEEE International Conference 
on Integrated Circuits, Design, and Verification, Hanoi, Vietnam, 2017, 
pp.82-87. DOI: 10.1109/ICDV.2017.8188644 
3. Dinh-Lam Tran, Xuan-Tu Tran, Duy-Hieu Bui, Cong-Kha Pham. An 
Efficient Hardware Implementation of Residual Data Binarization in HEVC 
CABAC Encoder. Electronics, vol. 9, issue 4, p. 684, April 2020. ISSN 2079-
9292 (SCI, IF 2.412, Q1). DOI:10.3390/electronics9040684 
100 
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